1. Field of the Invention
The present invention relates to a memory circuit provided with a plurality of memory cells for storing information, and particularly to a memory circuit which is composed of memory cells of ferroelectric capacitors requiring no refresh operation.
2. Description of the Prior Art
FIG. 1 is a diagram to show a construction of a memory cell of a conventional memory integrated circuit using a ferroelectric capacitors.
In the above circuit construction, the writing operation of data is carried out, as shown in FIG. 2A, by setting an electric potential of a bit line 1B at a high electric potential (H level) or a low electric potential (L level) in accordance with the data to be stored, setting a field effect transistor 1 in the conducting state by elevating an electric potential of a word line 1W, setting a node 2 at an electric potential of the data, and applying a pulse signal .phi. to a clock line 1C. Thereby, a capacitor memory cell is constructed, and a direction of spontaneous polarization of a ferroelectric capacitors 3 composed of lead zircon-titanate (PZT) is determined in accordance with an electric potential of the data.
In the same drawing, for example, when a writing operation of H level data is carried out, and if the node 2 is in the H level state and the clock line 1C is in the L level state, an electric field in the ferroelectric capacitors 3 is applied in the direction of arrow 4, and the spontaneous polarization of the ferroelectric capacitors 3 is generated in parallel with this direction.
While, when a writing operation of L level data writing is carried out, and if the pulse signal .phi. of the H level is outputted onto the clock line 1C, the spontaneous polarization of the ferroelectric capacitor 3 is generated in the direction of arrow 5. Namely, the polarization direction of arrow 5 shows the data to be stored in the ferroelectric capacitor 3, and since this polarization is not changed even when a power source (not shown) is switched off, nonvolatile data storage can be realized.
To read the data stored in the ferroelectric capacitor 3 as the memory cell in the circuit, as shown in FIG. 2B, the clock line 1C is set at the L level to place the bit line 1B in the floating state of the H level, and the electric potential of the word line 1W is elevated, so that the transistor 1 in the memory cell so as to be accessed is in the conducting state. Thereby, the node 2 is set at the H level, and an electric field is applied in the direction of arrow 4 in the ferroelectric capacitor 3. Accordingly, when the polarization direction becomes the same as the direction of arrow 4, since the state is held, the electric potential of the bit line 1B is not changed.
However, when the polarization direction is the same as the direction of arrow 5, the polarization direction is inverted to be the direction of arrow 4. At this time, the electric potentials of the node 2 and the bit line 1B are reduced by an amount corresponding to the polarization inversion. In FIG. 2B, the amount of polarization inversion is shown by reference numeral 6. The reduction of the electric potential of the bit line 1B is amplified and outputted by a sense amplifier 7 connected to the bit line 1B.
Thereafter, to restore the amount of polarization inversion to the value originally generated at the reading operation, a pulse signal .phi. of H level is outputted onto the clock line 1C to restore the polarization state of the ferroelectric capacitor 3 to the original state (the direction designated by arrow 4), and then the next operation, for example, a rewriting operation is performed.
Moreover, it is preferred that the ferroelectric capacitor memory requires no periodical refresh operation as a dynamic memory. Namely, when the refresh operation is included in the circuit operation, the throughput is reduced and the electric power to be used must be increased. Moreover, it is desired that the data in the ferroelectric capacitor 3 is not lost during the supplying of a power source.
However, in case the memory cell is as mentioned above, data are occasionally lost when the refresh operation is not carried out.
Namely, in FIG. 1, when the clock line 1C is in the L level state after information as data to be stored is written in the ferroelectric capacitor 3 under the setting of the node 2 at the H level (in the polarization direction of arrow 4 in FIG. 1), since the substrate of the transistor 1 is normally connected to Vss, the level of the node 2 is reduced to the L level because of leakage current through the PN junction between the substrate and the source/drain.
Accordingly, when a clock pulse .phi. of H level is outputted onto the clock line 1C to write data in another memory cell, an electric field applied to the ferroelectric capacitor 3 becomes inverse to that of the data writing at the H level, so that the polarization is inverted (in the polarization direction designated by the arrow 5 in FIG. 1) to lose data. The reason is that the node 2 is shut off from the bit line 1B and will be at the L level when a pulse signal .phi. of H level is provided on the clock line 1C.